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Dogan Ulus
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First-order temporal logic monitoring with BDDs
K Havelund, D Peled, D Ulus
Formal Methods in System Design 56 (1), 1-21, 2020
802020
Timed pattern matching
D Ulus, T Ferrère, E Asarin, O Maler
International Conference on Formal Modeling and Analysis of Timed Systems …, 2014
752014
AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic
D Ničković, O Lebeltel, O Maler, T Ferrère, D Ulus
International Journal on Software Tools for Technology Transfer 22, 741-758, 2020
592020
Online timed pattern matching using derivatives
D Ulus, T Ferrère, E Asarin, O Maler
Tools and Algorithms for the Construction and Analysis of Systems: 22nd …, 2016
572016
Montre: A Tool for Monitoring Timed Regular Expressions
D Ulus
Computer Aided Verification: 29th International Conference, CAV 2017 …, 2017
472017
On the quantitative semantics of regular expressions over real-valued signals
A Bakhirkin, T Ferrère, O Maler, D Ulus
International Conference on Formal Modeling and Analysis of Timed Systems …, 2017
292017
Measuring with timed patterns
T Ferrère, O Maler, D Ničković, D Ulus
Computer Aided Verification: 27th International Conference, CAV 2015, San …, 2015
282015
Special session: Embedded software for robotics: Challenges and future directions
H Abbas, I Saha, Y Shoukry, R Ehlers, G Fainekos, R Gupta, R Majumdar, ...
2018 International Conference on Embedded Software (EMSOFT), 1-10, 2018
18*2018
DejaVu: a monitoring tool for first-order temporal logic
K Havelund, D Peled, D Ulus
2018 IEEE Workshop on Monitoring and Testing of Cyber-Physical Systems (MT …, 2018
172018
Timescales: A benchmark generator for MTL monitoring tools
D Ulus
Runtime Verification: 19th International Conference, RV 2019, Porto …, 2019
152019
Online monitoring of metric temporal logic using sequential networks
D Ulus
arXiv preprint arXiv:1901.00175, 2019
152019
Derivatives of quantitative regular expressions
R Alur, K Mamouras, D Ulus
Models, Algorithms, Logics and Tools: Essays Dedicated to Kim Guldstrand …, 2017
152017
Specifying timed patterns using temporal logic
D Ulus, O Maler
Proceedings of the 21st International Conference on Hybrid Systems …, 2018
142018
First-order Temporal Logic Monitoring with BDDs, FMCAD’17
K Havelund, D Peled, D Ulus
IEEE, 2017
102017
Reactive control meets runtime verification: A case study of navigation
D Ulus, C Belta
Runtime Verification: 19th International Conference, RV 2019, Porto …, 2019
92019
Combining the temporal and epistemic dimensions for MTL monitoring
E Asarin, O Maler, D Nickovic, D Ulus
International Conference on Formal Modeling and Analysis of Timed Systems …, 2017
72017
Using haloes in mixed-signal assertion based verification
D Ulus, A Sen
2012 IEEE International High Level Design Validation and Test Workshop …, 2012
62012
Sequential circuits from regular expressions revisited
D Ulus
arXiv preprint arXiv:1801.08979, 2018
52018
Pattern Matching with Time: Theory and Applications
D Ulus
Universite Grenoble-Alpes (UGA), 2018
42018
On the complexity of timed pattern matching
E Asarin, T Ferrère, D Ničković, D Ulus
International Conference on Formal Modeling and Analysis of Timed Systems, 15-31, 2021
22021
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